The present invention relates generally to silicon on insulator (SOI) wafers and more specifically to a new method and resulting structure for producing SOI wafers.
Prior art processings for producing silicon on insulator wafers have generally not had the desired thickness control. A typical example of manufacturing is illustrated in FIGS. 1A through 1D. A thin layer of silicon-germanium 12 is formed on a silicon wafer 10. A silicon layer 14 is epitaxially grown on the silicon-germanium layer 12 having an interface at surface 16 and an exposed surface 17. A silicon handle 20 with an insulative layer, for example silicon dioxide 18, is bonded to surface 17 of the epitaxial layer 14. The original wafer 10 is then removed using the silicon-germanium layer 12 as a removal or etch stop. Subsequently, the silicon-germanium layer 12 is removed by etching which also removes a portion of the epitaxial layer 14. Thus the ultimate thickness of the layer 14 is a function of the etching control versus the epitaxial growth control. The resulting surface modified 16' in which the devices are formed has defects resulting from the etching and removal processing steps. This is not a fresh virgin surface.
Another common problem with silicon on insulator substrates is that a back channel may be formed along surface 17 since substrate 20 can act as a gate with the insulative layer 18 acting as the gate insulator. As illustrated in FIG. 2 a parasitic back channel can form at the surface 17 which electrically connects the N+ diffusions 22. This is a serious problem in SOI CMOS devices when the thickness of the epitaxial layer 14 is such that the drain and source diffusions of the NMOS devices `bottom out` onto the buried oxide layer 18. Under conditions where ionizing radiation is present (such as in outer space, for instance) holes trapped in the buried oxide layer 18 can cause a parasitic channel to form at the surface 17 of the NMOS devices leading to circuit failure.
Thus it is an object of the present invention to provide a method for fabricating silicon on insulator wafers with improved thickness control.
It is another object of the present invention to provide silicon on insulator wafers wherein the surface on which devices are formed is of increased quality.
A still further object of the present invention is to provide a silicon on insulator wafer which is less susceptible to bottom channel formation.
These and other objects are achieved by bonding a second substrate to a silicon-germanium layer on a first substrate by an intermediate insulative layer. The first substrate is removed down to the silicon-germanium layer and the silicon layer is epitaxially formed on the silicon-germanium layer. The resulting exposed surface of the epitaxial formed layer is the surface in which the devices are to be formed. Thus the final thickness of the epitaxial layer is a function of epitaxial control and the surface in which the devices are to be prepared is a virgin, untreated surface.
Preferably the silicon-germanium layer is grown using MBE (molecular beam epitaxy) or CVD and has a composition of Si.sub.1-x Ge.sub.x, with x in the 0.2 to 0.4 range. The first and second substrates may be silicon. The silicon-germanium layer would have a thickness in the range of 100 to 3000 angstroms, the insulative layer would have a thickness range of 1000 angstroms to 4 microns and epitaxial silicon layer would have a thickness in the range of 1000 angstroms to 20 microns.
The resulting structure has the silicon-germanium layer between the epitaxial layer and the insulator. Strain caused by lattice mismatch between silicon and germanium atoms in the silicon-germanium layer lowers the minority carrier lifetime and therefore minimizes the back channel formation when the wafer is used to form CMOS devices.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.